`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:12:21 11/19/2013
// Design Name:   zero_count
// Module Name:   G:/Xilinx_Proj/H_264_test/test_bench.v
// Project Name:  H_264_test
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: zero_count
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_bench;

	// Inputs
	reg [15:0] data;

	// Outputs
	wire [3:0] count;
	reg [5:0]cnt;
	reg clk;
	reg rst;
	// Instantiate the Unit Under Test (UUT)
	zero_count uut (
		.data(data), 
		.count(count)
	);

	initial begin
		// Initialize Inputs
		data = 0;
		
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		 #100 rst=1; 
		 #100 rst=0; 
		 #100 rst=1; 
		 clk=0;
		 cnt=0;
	end
    
always begin #50 clk=~clk; end
  
always @(negedge rst or posedge clk) begin
		if(!rst) begin
			cnt<=0;
		end
		else begin
			case(cnt)
			0:begin
				data<=1'd0;cnt<=cnt+1'b1;
			end
			1:begin
				data<=16'd1;cnt<=cnt+1'b1;
			end
			2:begin
				data<=16'd2;cnt<=cnt+1'b1;
			end
			3:begin
				data<=16'd4;cnt<=cnt+1'b1;
			end
			4:begin
				data<=16'd8;cnt<=cnt+1'b1;
			end
			5:begin
				data<=16'd16;cnt<=cnt+1'b1;
			end
			6:begin
				data<=16'd32;cnt<=cnt+1'b1;
			end
			7:begin
				data<=16'd64;cnt<=cnt+1'b1;
			end
			8:begin
				data<=16'd128;cnt<=cnt+1'b1;
			end
			9:begin
				data<=16'd256;cnt<=cnt+1'b1;
			end
			10:begin
				data<=16'd512;cnt<=cnt+1'b1;
			end
			11:begin
				data<=16'd1024;cnt<=cnt+1'b1;
			end
			12:begin
				data<=16'd2048;cnt<=cnt+1'b1;
			end
			13:begin
				data<=16'd4096;cnt<=cnt+1'b1;
			end
			14:begin
				data<=16'd8192;cnt<=cnt+1'b1;
			end
			15:begin
				data<=16'd16384;cnt<=cnt+1'b1;
			end
			16:begin
				data<=16'd32768;cnt<=cnt+1'b1;
			end
			17:begin
				data<=16'd324;cnt<=cnt+1'b1;
			end
			18:begin
				data<=16'd3278;cnt<=cnt+1'b1;
			end
			19:begin
				data<=16'd50768;cnt<=cnt+1'b1;
			end
			20:begin
				data<=16'd16543;cnt<=6'd20;
			end
			endcase
		end
end	
		
endmodule

